Timing optimization is carried out here and there in the design process of semiconductor integrated circuit devices. Conventionally, corrections at RTL (Resistor-Transistor Level), addition of a logic cell, and replacement of a logic cell etc. have been performed. Addition and replacement of logic cells aims to adjust a speed of charging and discharging of a load by size changes of a transistor or by threshold switching of the transistor. For this reason, there has been a problem that the designing period is increased because back tracking of designs such as a logic re-synthesis or a function re-verification is posed when such correction is made.
Japanese Patent Application Laid-Open Publication No. 2003-338546 (Patent Document 1) discloses a method for dissolving a delay violation by means of narrowing or widening a distance between adjacent wirings (conventional art 1), or partly changing a material of an insulating film between adjacent wirings (conventional art 2) to solve such problems, aiming at changing a parasitic capacitance between adjacent wirings in a timing adjustment of a semiconductor integrated circuit device.
On the other hand, as the generation of the process of the semiconductor integrated circuit device progresses, an operation speed of a transistor increases, and at the same time a width of a wiring that connects transistors becomes narrower, and the distance between adjacent wirings becomes closer. The speed of the semiconductor integrated circuit device (LSI) has become to be, in larger percentage, rate-controlled by an RC delay of the wiring rather than a gate delay. To reduce wiring resistance, an aspect ratio (aspect ratio of a cross section) of wiring structure is taken by rectangle being long to the height direction, and thus parasitic capacitance between adjacent wirings is increased, and there is posed further increase of wiring RC delay.
According to the fact, various technologies for reducing the wiring delay have been proposed regarding a road map of a semiconductor device. One of them is parasitic capacitance reduction between wirings by means of development of lower dielectric constant (low-k) materials for an insulating film between wiring layers. In recent years, the progress of low dielectric constant has also being saturated, and although attention has been paid to the insulating film between wiring layers formed of a porous low-k material which is the insulating film obtained by applying porosity to the low-k interlayer insulation film in the next generation, a problem of reliability has remained from insufficient mechanical strength of the materials.
Consequently, an attention is paid to a technology called Air-Gap which leaves a void between adjacent wirings of the same layer as a next-generation wiring structure. Note that, this Air-Gap technology is disclosed in Japanese Patent Application Laid-Open Publication No. 2003-297918 (Patent Document 2).